SystemCrafter SC is a SystemC synthesis tool for Xilinx FPGAs. SystemCrafter SC generates RTL VHDL or Verilog for downstream synthesis to Xilinx FPGAs, and closes the verification gap by writing a structural SystemC output for simulation.
FlowVHDL parses your VHDL file and creates flowcharts of the processes, functions and procedures. This helps you to create a graphical documentation of your VHDL designs and to understand VHDL files developed by others.
ModelSim-Altera Edition software is licensed to support designs written in 100 percent VHDL and 100 percent Verilog language and does not support designs that are written in a combination of VHDL and Verilog language, also known as mixed HDL.
The logiRC Remote Controller Receiver is an IP core from the Xylon logicBRICKSTM IP library for Xilinx FPGAs. This IP core can be used within Man Machine Interfaces (MMI) that include system control by an IR remote controller.
This free utility generates HDL Sine Look Up Table Modules in Verilog or VHDL. The developer make no warranties, but it works wonders for us! Hope you like it. A great program with a great and easy to use interface.
The ISE Design Suite: System Edition provides a comprehensive suite of integrated development environment, software tools, configuration wizards, and IP that facilitates your design and utilizes all of the flexibility offered by a programmable platfo
X-HDL 4 is the premier Verilog VHDL bi-directional translator. X-HDL performs translation of even the most complex RTL/gate-level code efficiently and requiring few, if any, "hand tweaks" of the translated code.